News

Releases

Announcing the release of Xyce™ 6.8

November 6, 2017 — The Xyce™ team is pleased to announce the release of Xyce™ Version 6.8. This release fixes a number of bugs in Xyce™ 6.7 and includes improvements to existing features of Xyce™ 6.7. Please see the Release Notes for a complete list of new features and enhancements.

Highlights for Xyce Release 6.8 include the following.

  • Improved robustness of GMIN stepping and SPICE DC OP strategy.
  • Improved performance of the BSIM-CMG model.
  • Addition of the Piecewise Empirical Model (PEM) memristor model.
  • The CSV print format is now supported for homotopy and noise output.
  • Improved Gnuplot compatibility for .STEP data.
  • Improved handling of hierarchical ".lib" file parsing.

Announcing the release of Xyce™ 6.7

May 8, 2017 — The Xyce™ team is pleased to announce the release of Xyce™ Version 6.7. This release fixes a number of bugs in Xyce™ 6.6 and includes improvements to existing features of Xyce™ 6.6. Please see the Release Notes for a complete list of new features and enhancements.

Highlights for Xyce Release 6.7 include the following.

New Devices and Device Model Improvements

  • The HICUM Level 0 BJT model version 1.32 was added as Xyce BJT level 230.
  • The HICUM Level 2 BJT model version 2.34 was added as Xyce BJT level 234.
  • The Multiplicity Factor (M) is now supported for the R, L and C devices.
  • Power output is now supported for the component inductors in both linear and nonlinear mutual inductors (K device).

Interface Improvements

  • A "-randseed" command line argument has been added to allow the user to specify a seed for the
    random number generator that is used for the expression library’s "rand," "gauss," and "agauss" functions.
  • When any expression includes use of a random number function ("rand," "gauss," or "agauss"), or if
    "-randseed" is given, Xyce will output the seed that is being used for that run.

Deployment Improvements

  • The Xyce binary release for Windows is now a 64-bit executable. Binaries for all prior releases had been
    32-bit executables.

Announcing the release of Xyce™ 6.6

November 9, 2016 — The Xyce™ team is pleased to announce the release of Xyce™ Version 6.6. This release fixes a number of bugs in Xyce™ 6.5 and includes improvements to existing features of Xyce™ 6.5. Please see the Release Notes for a complete list of new features and enhancements.

Highlights for Xyce Release 6.6 include the following.

New Devices and Device Model Improvements

  • All Verilog-A-derived models now support lead currents, and many more devices support power output.
  • THE VBIC 1.2 (Level=10) MODEL IS NOW DEPRECATED, and will be removed in the next version of Xyce. Please use the VBIC 1.3 model (levels 11 and 12) instead.
  • The PSP MOSFET, BSIM6 MOSFET, and MEXTRAM BJT have been updated to more recent versions.
  • The Xyce/ADMS Verilog compiler back-end can now produce correct code for models that collapse
    internal nodes to ground based on model parameter values.
  • The legacy version (102.5) of the PSP MOSFET has been added to Xyce as a new MOSFET level
    102.
  • The BSIM-CMG model version 110.0.0 has been added to Xyce as a new MOSFET level 110.

Enhanced Solver Stability, Performance and Features

  • Improved performance of device evaluation and loading through the separation of device types.
  • Improved performance and scalability of parallel netlist parsing and device distribution.
  • Improved robustness of the internal KSparse solver by employing KLU for numeric factorization failures.
  • A new time step error-control method (MASKIVARS option), based on types of circuit variables.
  • Note: The BDF time integration method (METHOD=BDF or METHOD=6) is now deprecated.  It will be removed in version 6.7 of Xyce. The Trapezoid (METHOD=TRAP or METHOD=7) and Gear (METHOD=GEAR or METHOD=8) methods will be the only supported time integration methods in version 6.7.
  • Improved performance and accuracy of transient adjoint sensitivity analysis.

Interface Improvements

  • Remeasure now supports .CSV files and comma-delimited .PRN files.
  • New ERROR measure calculates the norm between the measured waveform and a “comparison waveform”
    specified in a file. The supported norms are L1, L2 and INFNORM.

Announcing the release of Xyce™ 6.5

June 8, 2016 — The Xyce™ team is pleased to announce the release of Xyce™ Version 6.5. This release fixes a number of bugs in Xyce™ 6.4 and includes improvements to existing features of Xyce™ 6.4. Please see the Release Notes for a complete list of new features and enhancements.

Highlights for Xyce Release 6.5 include the following.

New Devices and Device Model Improvements

  • BSIM6 and VBIC 1.3 enhancements with observed performance gains as high as 25% on some circuits.
  • Xyce/ADMS Verilog-A model compiler code generation enhancements: improved support for (initial model) and (initial instance) blocks.
  • Xyce/ADMS new feature: added support of white noise and flicker noise for use in small-signal noise analysis.
  • Noise models have been added for all devices generated from Verilog-A using ADMS, except for the FBH HBT model.
  • The JUNCAP200 diode model has been added as Diode level 200.
  • The MVS MOSFET model has been added as models level 2000 (ETSOI version and 2001 (HEMT version).
  • The BSIM3 and BSIM4 models can now output transconductance on the .PRINT line.
  • Support for tap-changing in the Power Grid Transformer model.

Enhanced Solver Stability, Performance and Features

  • Internal full-step Newton method is now the default for transient simulation, which improves memory efficiency and performance.
  • Xyce has been updated to use Trilinos 12.6.3.
  • Transient adjoint parameter sensitivities are now supported.

Interface Improvements

  • Improved support for RISE, FALL, CROSS and LAST qualifiers in .MEASURE statements.
  • Re-measure now supports .CSD files and .STEP with .TRAN.
  • Improved support for lead currents, expressions and power in .MEASURE and .FOUR statements.
  • Restart can now provide seamless checkpointing for all time integration methods.
  • Power calculations are now supported for the level 1 BJT.
  • Improved output for restart result interpolations.

Announcing the release of Xyce™ 6.4

January 19, 2016 — The Xyce™ team is pleased to announce the release of Xyce™ Version 6.4. This release fixes a number of bugs in Xyce™ 6.3 and includes improvements to existing features of Xyce™ 6.3. Please see the Release Notes for a complete list of new features and enhancements.

Highlights for Xyce Release 6.4 include the following.

New Devices and Device Model Improvements     

  • VBIC version 1.3, 3- and 4-terminal variants (Q levels 11 and 12)    
  • MEXTRAM 504.11 with self-heating (Q level 505)     
  • New memristor device using the Yakopcic model    
  • Support for Reactive Power limits in the Power Grid Generator Bus model.

Enhanced Solver Stability, Performance and Features    

  • The Kundert SPARSE linear solver has been added as a linear solver option
  • The netlist parser has been significantly refactored to reduce memory consumption and improve parsing speeds for large circuits
  • Improved Harmonic Balance (HB) robustness during the initial guess calculation
  • New Local truncation Error (LTE) criterions that use history information of signals improve time stepping for all time integrators
  • Oversampling capability for Harmonic Balance time domain output enables users to produce well-resolved time-domain outputs
  • Arclength continuation is now much more useful and robust
  • Sensitivity analysis can now allow multiple objective functions

Interface Improvements     

  • Power calculations supported for controlled-source devices (B,E,F,G and H)
  • Support for additional .MEASURE statement syntaxes
  • New output options, that allow the user to suppress the header and  footer of standard-format output files
  • Improved error handling during netlist parsing
  • Improved Harmonic Balance Output
  • Improved compatibility between Xyce and PSpice Digital Behavioral models, via support for the DIGINITSTATE option

Announcing the release of Xyce™ 6.3

July 20, 2015 — The Xyce™ team is pleased to announce the release of Xyce™ Version 6.3. This release fixes a number of bugs in Xyce™ 6.2 and includes improvements to existing features of Xyce™ 6.2. Please see the Release Notes for a complete list of new features and enhancements.

Highlights for Xyce Release 6.3 include:

  • Small signal noise analysis (.NOISE)
  • New devices (MEXTRAM version 504, BSIM 6.1.0 and TEAM Memristor added)
  • .DC operating point strategy now applies SPICE-like source-stepping if other attempts fail.
  • New devices (Branch, Bus shunt, Transformer and PV Generator Bus) for modeling steady-state power flow in electric power grids.
  • ADMS back-end enhanced to generate code for analytic sensitivity derivatives.
  • Support for measure statements when .STEP is used.
  • The ability to re-measure existing data in .PRN files.
  • New multi-tone Harmonic Balance capability.
  • ADMS back-end improved to support Verilog-A ternary operators more correctly.
  • Extensive bug fixes and usability improvements for .MEASURE. This includes user-configurable output precision, and more informative output to standard output and log files.

Announcing the release of Xyce™ 6.2

October 9, 2014 — The Xyce™ team is pleased to announce the release of Xyce™ Version 6.2. This release is a minor release that fixes a number of bugs in Xyce™ 6.1 and includes improvements to existing features of Xyce™ 6.1. Please see the Release Notes for a complete list of new features and enhancements.

Highlights for Xyce Release 6.2 include:

  • Calculation of transient direct sensitivities.
  • Support for lead current calculation and output for Harmonic Balance (HB) analysis.
  • Improved interpolation for both the Trapezoid and Gear time integrators.
  • Improved results output (.PRINT) capabilities.
  • New models for a lumped transmission line and a digital latch.
  • Fixes for nearly 60 bugs and enhancement requests.

Also associated with this release are updates to the web site. The Frequently Asked Questions page and the instructions for adding device models to Xyce™ through Verilog-A have been updated.

Announcing the release of Xyce™ 6.1

April 14, 2014 — The Xyce™ team is pleased to announce the release of Xyce™ Version 6.1. Highlights for Xyce™ Release 6.1 include improved robustness of harmonic balance analysis, and the introduction of parallel AC, harmonic balance, and MPDE analysis. The BSIM-CMG was added as a new device, in addition to new digital models. Also, a simplified device code interface allows for easier integration of user device models into the Xyce code base. See the Release Notes for a complete list of new features and enhancements.

Also associated with this release are several additions to the web site. First, we moved the instructions for Building Xyce™ to a web page rather supplying them as a pdf. Second, we added a Frequently Asked Questions page that we will continue to expand, making it a significant resource for the Xyce™ user community. Additionally, with the improved device code interface, we have provided instructions for adding new device models to Xyce™ through Verilog-A.

Finally, a new Google Groups page has been made available as a forum for members of the Xyce community to ask questions and discuss any topic related to Xyce, including installation, use and development.

Announcing the release of Xyce™ 6.0.1

February 5, 2014 — The Xyce™ team is pleased to announce the release of Xyce™ Version 6.0.1. This release is a patch release that fixes a number of small bugs in Xyce™ 6.0. Also included is a new option for turning off transient assisted harmonic balance for faster start-up of HB simulations on linear problems. Please see the Release Notes for a complete list of new features and enhancements.

Announcing the Open Source Release of the Xyce™ Parallel Electronic Simulator

October 30, 2013 — For the first time, Xyce™, Sandia National Laboratories' SPICE-compatible parallel circuit simulator, is available for free public download. Xyce™ has been developed internally at Sandia National Laboratories and funded by the National Nuclear Security Administration's Advanced Simulation and Computing (ASC) Campaign. In providing an Open Source version of Xyce™ to the external community, Sandia hopes to contribute a robust and modern electronic simulator to users and researchers in the field.

While designed to be SPICE-compatible, Xyce™ is not a derivative of SPICE. It was designed from scratch to be a parallel simulation code, written in C++ and using a message-passing implementation (MPI). Xyce™ also leverages Sandia’s open-source solver library, Trilinos, which includes a number of circuit-specific solvers, such as the KLU direct solver. With its modular and flexible design, Xyce™ applies abstract interfaces to enable easy development of different analysis types, solvers and models.

Xyce™ is compatible with SPICE-based codes, in that it supports a canonical set of SPICE compact models and standard SPICE analysis methods, such as steady-state (DCOP), transient (TRAN), and small-signal frequency domain (AC). However, Xyce™ goes beyond most SPICE-based codes in a number of ways, including support for a large number of non-traditional models, such as neuron and reaction network models. Xyce™ also supports several additional analysis methods, including Harmonic Balance, Multi-Time PDE and Model-Order Reduction methods.

In releasing Xyce™ to the public, the Xyce™ development team hopes to foster external collaborations and solicit feedback from the simulation community to make Xyce™ an even more robust and useful code. Please see the Contact Us page for contact information.

New Publications

Awards and Achievements

In 2008 the Xyce team received an R&D 100 Award.