# This file is generated by the script SetUpCtestFiles.py
# If possible, modify the script to fix any issues with the CMakeLists.txt files
# Or you can remove this header line to prevent this file from being overwritten

file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/power_vbic13_3T_gear.cir ${CMAKE_CURRENT_BINARY_DIR}/power_vbic13_3T_gear.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/power_vbic13_3T_gear.cir.sh ${CMAKE_CURRENT_BINARY_DIR}/power_vbic13_3T_gear.cir.sh ONLY_IF_DIFFERENT)
file(CHMOD ${CMAKE_CURRENT_BINARY_DIR}/power_vbic13_3T_gear.cir.sh PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/power_vbic13_3T_gear.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/power_vbic13_3T_gear.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/power_vbic13_4T_gear.cir ${CMAKE_CURRENT_BINARY_DIR}/power_vbic13_4T_gear.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/power_vbic13_4T_gear.cir.sh ${CMAKE_CURRENT_BINARY_DIR}/power_vbic13_4T_gear.cir.sh ONLY_IF_DIFFERENT)
file(CHMOD ${CMAKE_CURRENT_BINARY_DIR}/power_vbic13_4T_gear.cir.sh PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/power_vbic13_4T_gear.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/power_vbic13_4T_gear.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/power_mextram_gear.cir ${CMAKE_CURRENT_BINARY_DIR}/power_mextram_gear.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/power_mextram_gear.cir.sh ${CMAKE_CURRENT_BINARY_DIR}/power_mextram_gear.cir.sh ONLY_IF_DIFFERENT)
file(CHMOD ${CMAKE_CURRENT_BINARY_DIR}/power_mextram_gear.cir.sh PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/power_mextram_gear.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/power_mextram_gear.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/power_juncap200_gear.cir ${CMAKE_CURRENT_BINARY_DIR}/power_juncap200_gear.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/power_juncap200_gear.cir.sh ${CMAKE_CURRENT_BINARY_DIR}/power_juncap200_gear.cir.sh ONLY_IF_DIFFERENT)
file(CHMOD ${CMAKE_CURRENT_BINARY_DIR}/power_juncap200_gear.cir.sh PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/power_juncap200_gear.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/power_juncap200_gear.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/power_bsim6_gear.cir ${CMAKE_CURRENT_BINARY_DIR}/power_bsim6_gear.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/power_bsim6_gear.cir.sh ${CMAKE_CURRENT_BINARY_DIR}/power_bsim6_gear.cir.sh ONLY_IF_DIFFERENT)
file(CHMOD ${CMAKE_CURRENT_BINARY_DIR}/power_bsim6_gear.cir.sh PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/power_bsim6_gear.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/power_bsim6_gear.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/modelcard_xyce.nmos ${CMAKE_CURRENT_BINARY_DIR}/modelcard_xyce.nmos ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/modelcard_xyce.pmos ${CMAKE_CURRENT_BINARY_DIR}/modelcard_xyce.pmos ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/tags ${CMAKE_CURRENT_BINARY_DIR}/tags ONLY_IF_DIFFERENT)
if( (NOT Xyce_PARALLEL_MPI) AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_POWER/power_bsim6_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} power_bsim6_gear.cir.sh $<TARGET_FILE:Xyce> ${XYCE_VERIFY} ${XYCE_VERIFY} power_bsim6_gear.cir ${OutputDataDir}/Verilog_POWER/power_bsim6_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_POWER/power_bsim6_gear.cir.sh PROPERTY LABELS "nightly;serial;parallel;power;valgrind;bsim6;adms")
endif()
if( Xyce_PARALLEL_MPI  AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_POWER/power_bsim6_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} power_bsim6_gear.cir.sh "mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce>" ${XYCE_VERIFY} ${XYCE_VERIFY} power_bsim6_gear.cir ${OutputDataDir}/Verilog_POWER/power_bsim6_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_POWER/power_bsim6_gear.cir.sh PROPERTY LABELS "nightly;serial;parallel;power;valgrind;bsim6;adms")
endif()
if( (NOT Xyce_PARALLEL_MPI) AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_POWER/power_juncap200_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} power_juncap200_gear.cir.sh $<TARGET_FILE:Xyce> ${XYCE_VERIFY} ${XYCE_VERIFY} power_juncap200_gear.cir ${OutputDataDir}/Verilog_POWER/power_juncap200_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_POWER/power_juncap200_gear.cir.sh PROPERTY LABELS "nightly;serial;parallel;power;valgrind;adms")
endif()
if( Xyce_PARALLEL_MPI  AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_POWER/power_juncap200_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} power_juncap200_gear.cir.sh "mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce>" ${XYCE_VERIFY} ${XYCE_VERIFY} power_juncap200_gear.cir ${OutputDataDir}/Verilog_POWER/power_juncap200_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_POWER/power_juncap200_gear.cir.sh PROPERTY LABELS "nightly;serial;parallel;power;valgrind;adms")
endif()
if( (NOT Xyce_PARALLEL_MPI) AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_POWER/power_mextram_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} power_mextram_gear.cir.sh $<TARGET_FILE:Xyce> ${XYCE_VERIFY} ${XYCE_VERIFY} power_mextram_gear.cir ${OutputDataDir}/Verilog_POWER/power_mextram_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_POWER/power_mextram_gear.cir.sh PROPERTY LABELS "nightly;serial;parallel;power;gear;adms")
endif()
if( Xyce_PARALLEL_MPI  AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_POWER/power_mextram_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} power_mextram_gear.cir.sh "mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce>" ${XYCE_VERIFY} ${XYCE_VERIFY} power_mextram_gear.cir ${OutputDataDir}/Verilog_POWER/power_mextram_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_POWER/power_mextram_gear.cir.sh PROPERTY LABELS "nightly;serial;parallel;power;gear;adms")
endif()
if( (NOT Xyce_PARALLEL_MPI) AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_POWER/power_vbic13_3T_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} power_vbic13_3T_gear.cir.sh $<TARGET_FILE:Xyce> ${XYCE_VERIFY} ${XYCE_VERIFY} power_vbic13_3T_gear.cir ${OutputDataDir}/Verilog_POWER/power_vbic13_3T_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_POWER/power_vbic13_3T_gear.cir.sh PROPERTY LABELS "nightly;serial;parallel;power;gear;vbic;adms")
endif()
if( Xyce_PARALLEL_MPI  AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_POWER/power_vbic13_3T_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} power_vbic13_3T_gear.cir.sh "mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce>" ${XYCE_VERIFY} ${XYCE_VERIFY} power_vbic13_3T_gear.cir ${OutputDataDir}/Verilog_POWER/power_vbic13_3T_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_POWER/power_vbic13_3T_gear.cir.sh PROPERTY LABELS "nightly;serial;parallel;power;gear;vbic;adms")
endif()
if( (NOT Xyce_PARALLEL_MPI) AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_POWER/power_vbic13_4T_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} power_vbic13_4T_gear.cir.sh $<TARGET_FILE:Xyce> ${XYCE_VERIFY} ${XYCE_VERIFY} power_vbic13_4T_gear.cir ${OutputDataDir}/Verilog_POWER/power_vbic13_4T_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_POWER/power_vbic13_4T_gear.cir.sh PROPERTY LABELS "nightly;serial;parallel;power;gear;vbic;adms")
endif()
if( Xyce_PARALLEL_MPI  AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_POWER/power_vbic13_4T_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} power_vbic13_4T_gear.cir.sh "mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce>" ${XYCE_VERIFY} ${XYCE_VERIFY} power_vbic13_4T_gear.cir ${OutputDataDir}/Verilog_POWER/power_vbic13_4T_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_POWER/power_vbic13_4T_gear.cir.sh PROPERTY LABELS "nightly;serial;parallel;power;gear;vbic;adms")
endif()
