# This file is generated by the script SetUpCtestFiles.py
# If possible, modify the script to fix any issues with the CMakeLists.txt files
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file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/lead_juncap200_gear.cir ${CMAKE_CURRENT_BINARY_DIR}/lead_juncap200_gear.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/lead_juncap200_gear.cir.sh ${CMAKE_CURRENT_BINARY_DIR}/lead_juncap200_gear.cir.sh ONLY_IF_DIFFERENT)
file(CHMOD ${CMAKE_CURRENT_BINARY_DIR}/lead_juncap200_gear.cir.sh PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE)
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file(CHMOD ${CMAKE_CURRENT_BINARY_DIR}/lead_psp_nmos_gear.cir.sh PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE)
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file(CHMOD ${CMAKE_CURRENT_BINARY_DIR}/lead_psp_pmos_gear.cir.sh PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/lead_vbic_4t_gear.cir ${CMAKE_CURRENT_BINARY_DIR}/lead_vbic_4t_gear.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/lead_vbic_4t_gear.cir.sh ${CMAKE_CURRENT_BINARY_DIR}/lead_vbic_4t_gear.cir.sh ONLY_IF_DIFFERENT)
file(CHMOD ${CMAKE_CURRENT_BINARY_DIR}/lead_vbic_4t_gear.cir.sh PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE)
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file(CHMOD ${CMAKE_CURRENT_BINARY_DIR}/lead_vbic_gear.cir.sh PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE)
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file(CHMOD ${CMAKE_CURRENT_BINARY_DIR}/lead_mextram_gear.cir.sh PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/lead_bsim6_gear.cir ${CMAKE_CURRENT_BINARY_DIR}/lead_bsim6_gear.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/lead_bsim6_gear.cir.sh ${CMAKE_CURRENT_BINARY_DIR}/lead_bsim6_gear.cir.sh ONLY_IF_DIFFERENT)
file(CHMOD ${CMAKE_CURRENT_BINARY_DIR}/lead_bsim6_gear.cir.sh PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/lead_bsimcmg_gear.cir ${CMAKE_CURRENT_BINARY_DIR}/lead_bsimcmg_gear.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/lead_bsimcmg_gear.cir.sh ${CMAKE_CURRENT_BINARY_DIR}/lead_bsimcmg_gear.cir.sh ONLY_IF_DIFFERENT)
file(CHMOD ${CMAKE_CURRENT_BINARY_DIR}/lead_bsimcmg_gear.cir.sh PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/tags ${CMAKE_CURRENT_BINARY_DIR}/tags ONLY_IF_DIFFERENT)
if( (NOT Xyce_PARALLEL_MPI) AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_bsim6_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} lead_bsim6_gear.cir.sh $<TARGET_FILE:Xyce> ${XYCE_VERIFY} ${XYCE_VERIFY} lead_bsim6_gear.cir ${OutputDataDir}/Verilog_LEAD_CURRENTS/lead_bsim6_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_bsim6_gear.cir.sh PROPERTY LABELS "serial;parallel;nightly;adms;leadcurrents")
endif()
if( Xyce_PARALLEL_MPI  AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_bsim6_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} lead_bsim6_gear.cir.sh "mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce>" ${XYCE_VERIFY} ${XYCE_VERIFY} lead_bsim6_gear.cir ${OutputDataDir}/Verilog_LEAD_CURRENTS/lead_bsim6_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_bsim6_gear.cir.sh PROPERTY LABELS "serial;parallel;nightly;adms;leadcurrents")
endif()
if( (NOT Xyce_PARALLEL_MPI) AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_bsimcmg_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} lead_bsimcmg_gear.cir.sh $<TARGET_FILE:Xyce> ${XYCE_VERIFY} ${XYCE_VERIFY} lead_bsimcmg_gear.cir ${OutputDataDir}/Verilog_LEAD_CURRENTS/lead_bsimcmg_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_bsimcmg_gear.cir.sh PROPERTY LABELS "serial;parallel;nightly;adms;leadcurrents")
endif()
if( Xyce_PARALLEL_MPI  AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_bsimcmg_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} lead_bsimcmg_gear.cir.sh "mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce>" ${XYCE_VERIFY} ${XYCE_VERIFY} lead_bsimcmg_gear.cir ${OutputDataDir}/Verilog_LEAD_CURRENTS/lead_bsimcmg_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_bsimcmg_gear.cir.sh PROPERTY LABELS "serial;parallel;nightly;adms;leadcurrents")
endif()
if( (NOT Xyce_PARALLEL_MPI) AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_juncap200_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} lead_juncap200_gear.cir.sh $<TARGET_FILE:Xyce> ${XYCE_VERIFY} ${XYCE_VERIFY} lead_juncap200_gear.cir ${OutputDataDir}/Verilog_LEAD_CURRENTS/lead_juncap200_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_juncap200_gear.cir.sh PROPERTY LABELS "serial;parallel;nightly;adms;leadcurrents")
endif()
if( Xyce_PARALLEL_MPI  AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_juncap200_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} lead_juncap200_gear.cir.sh "mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce>" ${XYCE_VERIFY} ${XYCE_VERIFY} lead_juncap200_gear.cir ${OutputDataDir}/Verilog_LEAD_CURRENTS/lead_juncap200_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_juncap200_gear.cir.sh PROPERTY LABELS "serial;parallel;nightly;adms;leadcurrents")
endif()
if( (NOT Xyce_PARALLEL_MPI) AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_mextram_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} lead_mextram_gear.cir.sh $<TARGET_FILE:Xyce> ${XYCE_VERIFY} ${XYCE_VERIFY} lead_mextram_gear.cir ${OutputDataDir}/Verilog_LEAD_CURRENTS/lead_mextram_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_mextram_gear.cir.sh PROPERTY LABELS "serial;parallel;nightly;adms;leadcurrents")
endif()
if( Xyce_PARALLEL_MPI  AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_mextram_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} lead_mextram_gear.cir.sh "mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce>" ${XYCE_VERIFY} ${XYCE_VERIFY} lead_mextram_gear.cir ${OutputDataDir}/Verilog_LEAD_CURRENTS/lead_mextram_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_mextram_gear.cir.sh PROPERTY LABELS "serial;parallel;nightly;adms;leadcurrents")
endif()
if( (NOT Xyce_PARALLEL_MPI) AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_psp_nmos_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} lead_psp_nmos_gear.cir.sh $<TARGET_FILE:Xyce> ${XYCE_VERIFY} ${XYCE_VERIFY} lead_psp_nmos_gear.cir ${OutputDataDir}/Verilog_LEAD_CURRENTS/lead_psp_nmos_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_psp_nmos_gear.cir.sh PROPERTY LABELS "serial;parallel;nightly;adms;leadcurrents")
endif()
if( Xyce_PARALLEL_MPI  AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_psp_nmos_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} lead_psp_nmos_gear.cir.sh "mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce>" ${XYCE_VERIFY} ${XYCE_VERIFY} lead_psp_nmos_gear.cir ${OutputDataDir}/Verilog_LEAD_CURRENTS/lead_psp_nmos_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_psp_nmos_gear.cir.sh PROPERTY LABELS "serial;parallel;nightly;adms;leadcurrents")
endif()
if( (NOT Xyce_PARALLEL_MPI) AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_psp_pmos_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} lead_psp_pmos_gear.cir.sh $<TARGET_FILE:Xyce> ${XYCE_VERIFY} ${XYCE_VERIFY} lead_psp_pmos_gear.cir ${OutputDataDir}/Verilog_LEAD_CURRENTS/lead_psp_pmos_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_psp_pmos_gear.cir.sh PROPERTY LABELS "serial;parallel;nightly;adms;leadcurrents")
endif()
if( Xyce_PARALLEL_MPI  AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_psp_pmos_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} lead_psp_pmos_gear.cir.sh "mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce>" ${XYCE_VERIFY} ${XYCE_VERIFY} lead_psp_pmos_gear.cir ${OutputDataDir}/Verilog_LEAD_CURRENTS/lead_psp_pmos_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_psp_pmos_gear.cir.sh PROPERTY LABELS "serial;parallel;nightly;adms;leadcurrents")
endif()
if( (NOT Xyce_PARALLEL_MPI) AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_vbic_4t_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} lead_vbic_4t_gear.cir.sh $<TARGET_FILE:Xyce> ${XYCE_VERIFY} ${XYCE_VERIFY} lead_vbic_4t_gear.cir ${OutputDataDir}/Verilog_LEAD_CURRENTS/lead_vbic_4t_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_vbic_4t_gear.cir.sh PROPERTY LABELS "serial;parallel;nightly;adms;leadcurrents")
endif()
if( Xyce_PARALLEL_MPI  AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_vbic_4t_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} lead_vbic_4t_gear.cir.sh "mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce>" ${XYCE_VERIFY} ${XYCE_VERIFY} lead_vbic_4t_gear.cir ${OutputDataDir}/Verilog_LEAD_CURRENTS/lead_vbic_4t_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_vbic_4t_gear.cir.sh PROPERTY LABELS "serial;parallel;nightly;adms;leadcurrents")
endif()
if( (NOT Xyce_PARALLEL_MPI) AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_vbic_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} lead_vbic_gear.cir.sh $<TARGET_FILE:Xyce> ${XYCE_VERIFY} ${XYCE_VERIFY} lead_vbic_gear.cir ${OutputDataDir}/Verilog_LEAD_CURRENTS/lead_vbic_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_vbic_gear.cir.sh PROPERTY LABELS "serial;parallel;nightly;adms;leadcurrents")
endif()
if( Xyce_PARALLEL_MPI  AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_vbic_gear.cir.sh COMMAND perl -I${XyceRegressionTestScripts} lead_vbic_gear.cir.sh "mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce>" ${XYCE_VERIFY} ${XYCE_VERIFY} lead_vbic_gear.cir ${OutputDataDir}/Verilog_LEAD_CURRENTS/lead_vbic_gear.cir.prn )
  set_property(TEST ${TestNamePrefix}Verilog_LEAD_CURRENTS/lead_vbic_gear.cir.sh PROPERTY LABELS "serial;parallel;nightly;adms;leadcurrents")
endif()
