# This file is generated by the script SetUpCtestFiles.py
# If possible, modify the script to fix any issues with the CMakeLists.txt files
# Or you can remove this header line to prevent this file from being overwritten

file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/arom.cir ${CMAKE_CURRENT_BINARY_DIR}/arom.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/arom.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/arom.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/b330.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/b330.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/counter.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/counter.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gm1.cir ${CMAKE_CURRENT_BINARY_DIR}/gm1.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gm1.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/gm1.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gm17.cir ${CMAKE_CURRENT_BINARY_DIR}/gm17.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gm17.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/gm17.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gm19.cir ${CMAKE_CURRENT_BINARY_DIR}/gm19.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gm19.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/gm19.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gm2.cir ${CMAKE_CURRENT_BINARY_DIR}/gm2.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gm2.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/gm2.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gm3.cir ${CMAKE_CURRENT_BINARY_DIR}/gm3.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gm3.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/gm3.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/jge.cir ${CMAKE_CURRENT_BINARY_DIR}/jge.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/jge.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/jge.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/mike2.cir ${CMAKE_CURRENT_BINARY_DIR}/mike2.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/mike2.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/mike2.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/rich3.cir ${CMAKE_CURRENT_BINARY_DIR}/rich3.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/rich3.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/rich3.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/todd3.cir ${CMAKE_CURRENT_BINARY_DIR}/todd3.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/todd3.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/todd3.cir.tags ONLY_IF_DIFFERENT)
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS3/gm1.cir COMMAND $<TARGET_FILE:Xyce> gm1.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS3/gm1.cir PROPERTY LABELS "circuitsim90;serial;nightly;mos3")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS3/gm1.cir PROPERTIES FIXTURES_SETUP gm1.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS3/gm1.cir.verify COMMAND ${XYCE_VERIFY} gm1.cir ${OutputDataDir}/CircuitSim90/MOS3/gm1.cir.prn gm1.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS3/gm1.cir.verify PROPERTIES FIXTURES_REQUIRED gm1.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS3/gm1.cir.verify PROPERTY LABELS "circuitsim90;serial;nightly;mos3")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS3/gm17.cir COMMAND $<TARGET_FILE:Xyce> gm17.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS3/gm17.cir PROPERTY LABELS "circuitsim90;serial;nightly;mos3")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS3/gm17.cir PROPERTIES FIXTURES_SETUP gm17.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS3/gm17.cir.verify COMMAND ${XYCE_VERIFY} gm17.cir ${OutputDataDir}/CircuitSim90/MOS3/gm17.cir.prn gm17.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS3/gm17.cir.verify PROPERTIES FIXTURES_REQUIRED gm17.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS3/gm17.cir.verify PROPERTY LABELS "circuitsim90;serial;nightly;mos3")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS3/gm2.cir COMMAND $<TARGET_FILE:Xyce> gm2.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS3/gm2.cir PROPERTY LABELS "circuitsim90;serial;nightly;mos3")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS3/gm2.cir PROPERTIES FIXTURES_SETUP gm2.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS3/gm2.cir.verify COMMAND ${XYCE_VERIFY} gm2.cir ${OutputDataDir}/CircuitSim90/MOS3/gm2.cir.prn gm2.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS3/gm2.cir.verify PROPERTIES FIXTURES_REQUIRED gm2.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS3/gm2.cir.verify PROPERTY LABELS "circuitsim90;serial;nightly;mos3")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS3/gm3.cir COMMAND $<TARGET_FILE:Xyce> gm3.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS3/gm3.cir PROPERTY LABELS "circuitsim90;serial;nightly;mos3")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS3/gm3.cir PROPERTIES FIXTURES_SETUP gm3.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS3/gm3.cir.verify COMMAND ${XYCE_VERIFY} gm3.cir ${OutputDataDir}/CircuitSim90/MOS3/gm3.cir.prn gm3.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS3/gm3.cir.verify PROPERTIES FIXTURES_REQUIRED gm3.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS3/gm3.cir.verify PROPERTY LABELS "circuitsim90;serial;nightly;mos3")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS3/mike2.cir COMMAND $<TARGET_FILE:Xyce> mike2.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS3/mike2.cir PROPERTY LABELS "circuitsim90;serial;nightly;mos3")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS3/mike2.cir PROPERTIES FIXTURES_SETUP mike2.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS3/mike2.cir.verify COMMAND ${XYCE_VERIFY} mike2.cir ${OutputDataDir}/CircuitSim90/MOS3/mike2.cir.prn mike2.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS3/mike2.cir.verify PROPERTIES FIXTURES_REQUIRED mike2.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS3/mike2.cir.verify PROPERTY LABELS "circuitsim90;serial;nightly;mos3")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS3/todd3.cir COMMAND $<TARGET_FILE:Xyce> todd3.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS3/todd3.cir PROPERTY LABELS "circuitsim90;serial;nightly;mos3")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS3/todd3.cir PROPERTIES FIXTURES_SETUP todd3.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS3/todd3.cir.verify COMMAND ${XYCE_VERIFY} todd3.cir ${OutputDataDir}/CircuitSim90/MOS3/todd3.cir.prn todd3.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS3/todd3.cir.verify PROPERTIES FIXTURES_REQUIRED todd3.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS3/todd3.cir.verify PROPERTY LABELS "circuitsim90;serial;nightly;mos3")
endif()
