# This file is generated by the script SetUpCtestFiles.py
# If possible, modify the script to fix any issues with the CMakeLists.txt files
# Or you can remove this header line to prevent this file from being overwritten

file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/ab_ac.cir ${CMAKE_CURRENT_BINARY_DIR}/ab_ac.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/ab_ac.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/ab_ac.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/ab_integ.cir ${CMAKE_CURRENT_BINARY_DIR}/ab_integ.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/ab_integ.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/ab_integ.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/ab_opamp.cir ${CMAKE_CURRENT_BINARY_DIR}/ab_opamp.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/ab_opamp.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/ab_opamp.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/cram.cir ${CMAKE_CURRENT_BINARY_DIR}/cram.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/cram.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/cram.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/e1480.cir ${CMAKE_CURRENT_BINARY_DIR}/e1480.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/e1480.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/e1480.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/g1310.cir ${CMAKE_CURRENT_BINARY_DIR}/g1310.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/g1310.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/g1310.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gm6.cir ${CMAKE_CURRENT_BINARY_DIR}/gm6.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gm6.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/gm6.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/hussamp.cir ${CMAKE_CURRENT_BINARY_DIR}/hussamp.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/hussamp.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/hussamp.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/mosrect.cir ${CMAKE_CURRENT_BINARY_DIR}/mosrect.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/mosrect.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/mosrect.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/mux8.cir ${CMAKE_CURRENT_BINARY_DIR}/mux8.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/mux8.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/mux8.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/nand.cir ${CMAKE_CURRENT_BINARY_DIR}/nand.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/nand.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/nand.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/pump.cir ${CMAKE_CURRENT_BINARY_DIR}/pump.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/pump.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/pump.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/reg0.cir ${CMAKE_CURRENT_BINARY_DIR}/reg0.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/reg0.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/reg0.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/ring.cir ${CMAKE_CURRENT_BINARY_DIR}/ring.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/ring.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/ring.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/schmitfast.cir ${CMAKE_CURRENT_BINARY_DIR}/schmitfast.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/schmitfast.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/schmitfast.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/schmitslow.cir ${CMAKE_CURRENT_BINARY_DIR}/schmitslow.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/schmitslow.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/schmitslow.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/slowlatch.cir ${CMAKE_CURRENT_BINARY_DIR}/slowlatch.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/slowlatch.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/slowlatch.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/toronto.cir ${CMAKE_CURRENT_BINARY_DIR}/toronto.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/toronto.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/toronto.cir.tags ONLY_IF_DIFFERENT)
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/ab_integ.cir COMMAND $<TARGET_FILE:Xyce> ab_integ.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/ab_integ.cir PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/ab_integ.cir PROPERTIES FIXTURES_SETUP ab_integ.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/ab_integ.cir.verify COMMAND ${XYCE_VERIFY} ab_integ.cir ${OutputDataDir}/CircuitSim90/MOS2/ab_integ.cir.prn ab_integ.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/ab_integ.cir.verify PROPERTIES FIXTURES_REQUIRED ab_integ.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/ab_integ.cir.verify PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/e1480.cir COMMAND $<TARGET_FILE:Xyce> e1480.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/e1480.cir PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/e1480.cir PROPERTIES FIXTURES_SETUP e1480.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/e1480.cir.verify COMMAND ${XYCE_VERIFY} e1480.cir ${OutputDataDir}/CircuitSim90/MOS2/e1480.cir.prn e1480.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/e1480.cir.verify PROPERTIES FIXTURES_REQUIRED e1480.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/e1480.cir.verify PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/g1310.cir COMMAND $<TARGET_FILE:Xyce> g1310.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/g1310.cir PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/g1310.cir PROPERTIES FIXTURES_SETUP g1310.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/g1310.cir.verify COMMAND ${XYCE_VERIFY} g1310.cir ${OutputDataDir}/CircuitSim90/MOS2/g1310.cir.prn g1310.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/g1310.cir.verify PROPERTIES FIXTURES_REQUIRED g1310.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/g1310.cir.verify PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/gm6.cir COMMAND $<TARGET_FILE:Xyce> gm6.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/gm6.cir PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/gm6.cir PROPERTIES FIXTURES_SETUP gm6.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/gm6.cir.verify COMMAND ${XYCE_VERIFY} gm6.cir ${OutputDataDir}/CircuitSim90/MOS2/gm6.cir.prn gm6.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/gm6.cir.verify PROPERTIES FIXTURES_REQUIRED gm6.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/gm6.cir.verify PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/hussamp.cir COMMAND $<TARGET_FILE:Xyce> hussamp.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/hussamp.cir PROPERTY LABELS "circuitsim90;serial;nightly;nodeset;mos2;op")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/hussamp.cir PROPERTIES FIXTURES_SETUP hussamp.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/hussamp.cir.verify COMMAND ${XYCE_VERIFY} hussamp.cir ${OutputDataDir}/CircuitSim90/MOS2/hussamp.cir.prn hussamp.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/hussamp.cir.verify PROPERTIES FIXTURES_REQUIRED hussamp.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/hussamp.cir.verify PROPERTY LABELS "circuitsim90;serial;nightly;nodeset;mos2;op")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/mosrect.cir COMMAND $<TARGET_FILE:Xyce> mosrect.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/mosrect.cir PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/mosrect.cir PROPERTIES FIXTURES_SETUP mosrect.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/mosrect.cir.verify COMMAND ${XYCE_VERIFY} mosrect.cir ${OutputDataDir}/CircuitSim90/MOS2/mosrect.cir.prn mosrect.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/mosrect.cir.verify PROPERTIES FIXTURES_REQUIRED mosrect.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/mosrect.cir.verify PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/mux8.cir COMMAND $<TARGET_FILE:Xyce> mux8.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/mux8.cir PROPERTY LABELS "circuitsim90;serial;weekly;mos2")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/mux8.cir PROPERTIES FIXTURES_SETUP mux8.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/mux8.cir.verify COMMAND ${XYCE_VERIFY} mux8.cir ${OutputDataDir}/CircuitSim90/MOS2/mux8.cir.prn mux8.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/mux8.cir.verify PROPERTIES FIXTURES_REQUIRED mux8.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/mux8.cir.verify PROPERTY LABELS "circuitsim90;serial;weekly;mos2")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/nand.cir COMMAND $<TARGET_FILE:Xyce> nand.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/nand.cir PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/nand.cir PROPERTIES FIXTURES_SETUP nand.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/nand.cir.verify COMMAND ${XYCE_VERIFY} nand.cir ${OutputDataDir}/CircuitSim90/MOS2/nand.cir.prn nand.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/nand.cir.verify PROPERTIES FIXTURES_REQUIRED nand.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/nand.cir.verify PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/ring.cir COMMAND $<TARGET_FILE:Xyce> ring.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/ring.cir PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/ring.cir PROPERTIES FIXTURES_SETUP ring.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/ring.cir.verify COMMAND ${XYCE_VERIFY} ring.cir ${OutputDataDir}/CircuitSim90/MOS2/ring.cir.prn ring.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/ring.cir.verify PROPERTIES FIXTURES_REQUIRED ring.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/ring.cir.verify PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/slowlatch.cir COMMAND $<TARGET_FILE:Xyce> slowlatch.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/slowlatch.cir PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/slowlatch.cir PROPERTIES FIXTURES_SETUP slowlatch.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/slowlatch.cir.verify COMMAND ${XYCE_VERIFY} slowlatch.cir ${OutputDataDir}/CircuitSim90/MOS2/slowlatch.cir.prn slowlatch.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/slowlatch.cir.verify PROPERTIES FIXTURES_REQUIRED slowlatch.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/slowlatch.cir.verify PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/toronto.cir COMMAND $<TARGET_FILE:Xyce> toronto.cir )
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/toronto.cir PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/toronto.cir PROPERTIES FIXTURES_SETUP toronto.cir)
  add_test(NAME ${TestNamePrefix}CircuitSim90/MOS2/toronto.cir.verify COMMAND ${XYCE_VERIFY} toronto.cir ${OutputDataDir}/CircuitSim90/MOS2/toronto.cir.prn toronto.cir.prn )
  set_tests_properties(${TestNamePrefix}CircuitSim90/MOS2/toronto.cir.verify PROPERTIES FIXTURES_REQUIRED toronto.cir)
  set_property(TEST ${TestNamePrefix}CircuitSim90/MOS2/toronto.cir.verify PROPERTY LABELS "circuitsim90;serial;nightly;mos2")
endif()
