# This file is generated by the script SetUpCtestFiles.py
# If possible, modify the script to fix any issues with the CMakeLists.txt files
# Or you can remove this header line to prevent this file from being overwritten

file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gain-stage1-bsim4p7.cir ${CMAKE_CURRENT_BINARY_DIR}/gain-stage1-bsim4p7.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gain-stage1-bsim4p7.cir.sh ${CMAKE_CURRENT_BINARY_DIR}/gain-stage1-bsim4p7.cir.sh ONLY_IF_DIFFERENT)
file(CHMOD ${CMAKE_CURRENT_BINARY_DIR}/gain-stage1-bsim4p7.cir.sh PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gain-stage1-bsim4p7.cir.tags ${CMAKE_CURRENT_BINARY_DIR}/gain-stage1-bsim4p7.cir.tags ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/modelcard.noise.nmos ${CMAKE_CURRENT_BINARY_DIR}/modelcard.noise.nmos ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/test1.cir ${CMAKE_CURRENT_BINARY_DIR}/test1.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/test2.cir ${CMAKE_CURRENT_BINARY_DIR}/test2.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/test3.cir ${CMAKE_CURRENT_BINARY_DIR}/test3.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/test4.cir ${CMAKE_CURRENT_BINARY_DIR}/test4.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/test5.cir ${CMAKE_CURRENT_BINARY_DIR}/test5.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/test6.cir ${CMAKE_CURRENT_BINARY_DIR}/test6.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/test7.cir ${CMAKE_CURRENT_BINARY_DIR}/test7.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/test8.cir ${CMAKE_CURRENT_BINARY_DIR}/test8.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/test9.cir ${CMAKE_CURRENT_BINARY_DIR}/test9.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/test10.cir ${CMAKE_CURRENT_BINARY_DIR}/test10.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/test11.cir ${CMAKE_CURRENT_BINARY_DIR}/test11.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/test12.cir ${CMAKE_CURRENT_BINARY_DIR}/test12.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/test13.cir ${CMAKE_CURRENT_BINARY_DIR}/test13.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/test14.cir ${CMAKE_CURRENT_BINARY_DIR}/test14.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/modelcard.nmos ${CMAKE_CURRENT_BINARY_DIR}/modelcard.nmos ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/modelcard.pmos ${CMAKE_CURRENT_BINARY_DIR}/modelcard.pmos ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/tags ${CMAKE_CURRENT_BINARY_DIR}/tags ONLY_IF_DIFFERENT)
if( (NOT Xyce_PARALLEL_MPI) AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/gain-stage1-bsim4p7.cir.sh COMMAND perl -I${XyceRegressionTestScripts} gain-stage1-bsim4p7.cir.sh $<TARGET_FILE:Xyce> ${XYCE_VERIFY} ${XYCE_VERIFY} gain-stage1-bsim4p7.cir ${OutputDataDir}/BSIM4_v4p7/gain-stage1-bsim4p7.cir.prn )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/gain-stage1-bsim4p7.cir.sh PROPERTY LABELS "serial;parallel;nightly;bsim4;noise")
endif()
if( Xyce_PARALLEL_MPI  AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/gain-stage1-bsim4p7.cir.sh COMMAND perl -I${XyceRegressionTestScripts} gain-stage1-bsim4p7.cir.sh "mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce>" ${XYCE_VERIFY} ${XYCE_VERIFY} gain-stage1-bsim4p7.cir ${OutputDataDir}/BSIM4_v4p7/gain-stage1-bsim4p7.cir.prn )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/gain-stage1-bsim4p7.cir.sh PROPERTY LABELS "serial;parallel;nightly;bsim4;noise")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test1.cir COMMAND $<TARGET_FILE:Xyce> test1.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test1.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test1.cir PROPERTIES FIXTURES_SETUP test1.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test1.cir.verify COMMAND ${XYCE_VERIFY} test1.cir ${OutputDataDir}/BSIM4_v4p7/test1.cir.prn test1.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test1.cir.verify PROPERTIES FIXTURES_REQUIRED test1.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test1.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( Xyce_PARALLEL_MPI  )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test1.cir COMMAND mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce> test1.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test1.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test1.cir PROPERTIES FIXTURES_SETUP test1.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test1.cir.verify COMMAND ${XYCE_VERIFY} test1.cir ${OutputDataDir}/BSIM4_v4p7/test1.cir.prn test1.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test1.cir.verify PROPERTIES FIXTURES_REQUIRED test1.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test1.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test10.cir COMMAND $<TARGET_FILE:Xyce> test10.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test10.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test10.cir PROPERTIES FIXTURES_SETUP test10.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test10.cir.verify COMMAND ${XYCE_VERIFY} test10.cir ${OutputDataDir}/BSIM4_v4p7/test10.cir.prn test10.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test10.cir.verify PROPERTIES FIXTURES_REQUIRED test10.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test10.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( Xyce_PARALLEL_MPI  )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test10.cir COMMAND mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce> test10.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test10.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test10.cir PROPERTIES FIXTURES_SETUP test10.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test10.cir.verify COMMAND ${XYCE_VERIFY} test10.cir ${OutputDataDir}/BSIM4_v4p7/test10.cir.prn test10.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test10.cir.verify PROPERTIES FIXTURES_REQUIRED test10.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test10.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test11.cir COMMAND $<TARGET_FILE:Xyce> test11.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test11.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test11.cir PROPERTIES FIXTURES_SETUP test11.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test11.cir.verify COMMAND ${XYCE_VERIFY} test11.cir ${OutputDataDir}/BSIM4_v4p7/test11.cir.prn test11.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test11.cir.verify PROPERTIES FIXTURES_REQUIRED test11.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test11.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( Xyce_PARALLEL_MPI  )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test11.cir COMMAND mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce> test11.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test11.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test11.cir PROPERTIES FIXTURES_SETUP test11.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test11.cir.verify COMMAND ${XYCE_VERIFY} test11.cir ${OutputDataDir}/BSIM4_v4p7/test11.cir.prn test11.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test11.cir.verify PROPERTIES FIXTURES_REQUIRED test11.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test11.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test12.cir COMMAND $<TARGET_FILE:Xyce> test12.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test12.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test12.cir PROPERTIES FIXTURES_SETUP test12.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test12.cir.verify COMMAND ${XYCE_VERIFY} test12.cir ${OutputDataDir}/BSIM4_v4p7/test12.cir.prn test12.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test12.cir.verify PROPERTIES FIXTURES_REQUIRED test12.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test12.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( Xyce_PARALLEL_MPI  )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test12.cir COMMAND mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce> test12.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test12.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test12.cir PROPERTIES FIXTURES_SETUP test12.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test12.cir.verify COMMAND ${XYCE_VERIFY} test12.cir ${OutputDataDir}/BSIM4_v4p7/test12.cir.prn test12.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test12.cir.verify PROPERTIES FIXTURES_REQUIRED test12.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test12.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test13.cir COMMAND $<TARGET_FILE:Xyce> test13.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test13.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test13.cir PROPERTIES FIXTURES_SETUP test13.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test13.cir.verify COMMAND ${XYCE_VERIFY} test13.cir ${OutputDataDir}/BSIM4_v4p7/test13.cir.prn test13.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test13.cir.verify PROPERTIES FIXTURES_REQUIRED test13.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test13.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( Xyce_PARALLEL_MPI  )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test13.cir COMMAND mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce> test13.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test13.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test13.cir PROPERTIES FIXTURES_SETUP test13.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test13.cir.verify COMMAND ${XYCE_VERIFY} test13.cir ${OutputDataDir}/BSIM4_v4p7/test13.cir.prn test13.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test13.cir.verify PROPERTIES FIXTURES_REQUIRED test13.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test13.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test14.cir COMMAND $<TARGET_FILE:Xyce> test14.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test14.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test14.cir PROPERTIES FIXTURES_SETUP test14.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test14.cir.verify COMMAND ${XYCE_VERIFY} test14.cir ${OutputDataDir}/BSIM4_v4p7/test14.cir.prn test14.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test14.cir.verify PROPERTIES FIXTURES_REQUIRED test14.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test14.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( Xyce_PARALLEL_MPI  )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test14.cir COMMAND mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce> test14.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test14.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test14.cir PROPERTIES FIXTURES_SETUP test14.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test14.cir.verify COMMAND ${XYCE_VERIFY} test14.cir ${OutputDataDir}/BSIM4_v4p7/test14.cir.prn test14.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test14.cir.verify PROPERTIES FIXTURES_REQUIRED test14.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test14.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test2.cir COMMAND $<TARGET_FILE:Xyce> test2.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test2.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test2.cir PROPERTIES FIXTURES_SETUP test2.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test2.cir.verify COMMAND ${XYCE_VERIFY} test2.cir ${OutputDataDir}/BSIM4_v4p7/test2.cir.prn test2.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test2.cir.verify PROPERTIES FIXTURES_REQUIRED test2.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test2.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( Xyce_PARALLEL_MPI  )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test2.cir COMMAND mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce> test2.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test2.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test2.cir PROPERTIES FIXTURES_SETUP test2.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test2.cir.verify COMMAND ${XYCE_VERIFY} test2.cir ${OutputDataDir}/BSIM4_v4p7/test2.cir.prn test2.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test2.cir.verify PROPERTIES FIXTURES_REQUIRED test2.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test2.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test3.cir COMMAND $<TARGET_FILE:Xyce> test3.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test3.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test3.cir PROPERTIES FIXTURES_SETUP test3.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test3.cir.verify COMMAND ${XYCE_VERIFY} test3.cir ${OutputDataDir}/BSIM4_v4p7/test3.cir.prn test3.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test3.cir.verify PROPERTIES FIXTURES_REQUIRED test3.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test3.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( Xyce_PARALLEL_MPI  )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test3.cir COMMAND mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce> test3.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test3.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test3.cir PROPERTIES FIXTURES_SETUP test3.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test3.cir.verify COMMAND ${XYCE_VERIFY} test3.cir ${OutputDataDir}/BSIM4_v4p7/test3.cir.prn test3.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test3.cir.verify PROPERTIES FIXTURES_REQUIRED test3.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test3.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test4.cir COMMAND $<TARGET_FILE:Xyce> test4.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test4.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test4.cir PROPERTIES FIXTURES_SETUP test4.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test4.cir.verify COMMAND ${XYCE_VERIFY} test4.cir ${OutputDataDir}/BSIM4_v4p7/test4.cir.prn test4.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test4.cir.verify PROPERTIES FIXTURES_REQUIRED test4.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test4.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( Xyce_PARALLEL_MPI  )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test4.cir COMMAND mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce> test4.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test4.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test4.cir PROPERTIES FIXTURES_SETUP test4.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test4.cir.verify COMMAND ${XYCE_VERIFY} test4.cir ${OutputDataDir}/BSIM4_v4p7/test4.cir.prn test4.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test4.cir.verify PROPERTIES FIXTURES_REQUIRED test4.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test4.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test5.cir COMMAND $<TARGET_FILE:Xyce> test5.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test5.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test5.cir PROPERTIES FIXTURES_SETUP test5.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test5.cir.verify COMMAND ${XYCE_VERIFY} test5.cir ${OutputDataDir}/BSIM4_v4p7/test5.cir.prn test5.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test5.cir.verify PROPERTIES FIXTURES_REQUIRED test5.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test5.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( Xyce_PARALLEL_MPI  )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test5.cir COMMAND mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce> test5.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test5.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test5.cir PROPERTIES FIXTURES_SETUP test5.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test5.cir.verify COMMAND ${XYCE_VERIFY} test5.cir ${OutputDataDir}/BSIM4_v4p7/test5.cir.prn test5.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test5.cir.verify PROPERTIES FIXTURES_REQUIRED test5.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test5.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test6.cir COMMAND $<TARGET_FILE:Xyce> test6.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test6.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test6.cir PROPERTIES FIXTURES_SETUP test6.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test6.cir.verify COMMAND ${XYCE_VERIFY} test6.cir ${OutputDataDir}/BSIM4_v4p7/test6.cir.prn test6.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test6.cir.verify PROPERTIES FIXTURES_REQUIRED test6.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test6.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( Xyce_PARALLEL_MPI  )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test6.cir COMMAND mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce> test6.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test6.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test6.cir PROPERTIES FIXTURES_SETUP test6.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test6.cir.verify COMMAND ${XYCE_VERIFY} test6.cir ${OutputDataDir}/BSIM4_v4p7/test6.cir.prn test6.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test6.cir.verify PROPERTIES FIXTURES_REQUIRED test6.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test6.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test7.cir COMMAND $<TARGET_FILE:Xyce> test7.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test7.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test7.cir PROPERTIES FIXTURES_SETUP test7.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test7.cir.verify COMMAND ${XYCE_VERIFY} test7.cir ${OutputDataDir}/BSIM4_v4p7/test7.cir.prn test7.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test7.cir.verify PROPERTIES FIXTURES_REQUIRED test7.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test7.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( Xyce_PARALLEL_MPI  )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test7.cir COMMAND mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce> test7.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test7.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test7.cir PROPERTIES FIXTURES_SETUP test7.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test7.cir.verify COMMAND ${XYCE_VERIFY} test7.cir ${OutputDataDir}/BSIM4_v4p7/test7.cir.prn test7.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test7.cir.verify PROPERTIES FIXTURES_REQUIRED test7.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test7.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test8.cir COMMAND $<TARGET_FILE:Xyce> test8.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test8.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test8.cir PROPERTIES FIXTURES_SETUP test8.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test8.cir.verify COMMAND ${XYCE_VERIFY} test8.cir ${OutputDataDir}/BSIM4_v4p7/test8.cir.prn test8.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test8.cir.verify PROPERTIES FIXTURES_REQUIRED test8.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test8.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( Xyce_PARALLEL_MPI  )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test8.cir COMMAND mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce> test8.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test8.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test8.cir PROPERTIES FIXTURES_SETUP test8.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test8.cir.verify COMMAND ${XYCE_VERIFY} test8.cir ${OutputDataDir}/BSIM4_v4p7/test8.cir.prn test8.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test8.cir.verify PROPERTIES FIXTURES_REQUIRED test8.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test8.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( (NOT Xyce_PARALLEL_MPI) )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test9.cir COMMAND $<TARGET_FILE:Xyce> test9.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test9.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test9.cir PROPERTIES FIXTURES_SETUP test9.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test9.cir.verify COMMAND ${XYCE_VERIFY} test9.cir ${OutputDataDir}/BSIM4_v4p7/test9.cir.prn test9.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test9.cir.verify PROPERTIES FIXTURES_REQUIRED test9.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test9.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
if( Xyce_PARALLEL_MPI  )
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test9.cir COMMAND mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce> test9.cir )
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test9.cir PROPERTY LABELS "serial;parallel;nightly;bsim4")
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test9.cir PROPERTIES FIXTURES_SETUP test9.cir)
  add_test(NAME ${TestNamePrefix}BSIM4_v4p7/test9.cir.verify COMMAND ${XYCE_VERIFY} test9.cir ${OutputDataDir}/BSIM4_v4p7/test9.cir.prn test9.cir.prn )
  set_tests_properties(${TestNamePrefix}BSIM4_v4p7/test9.cir.verify PROPERTIES FIXTURES_REQUIRED test9.cir)
  set_property(TEST ${TestNamePrefix}BSIM4_v4p7/test9.cir.verify PROPERTY LABELS "serial;parallel;nightly;bsim4")
endif()
