# This file is generated by the script SetUpCtestFiles.py
# If possible, modify the script to fix any issues with the CMakeLists.txt files
# Or you can remove this header line to prevent this file from being overwritten

file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/exclude ${CMAKE_CURRENT_BINARY_DIR}/exclude ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gstage.cir ${CMAKE_CURRENT_BINARY_DIR}/gstage.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/gstage.cir.sh ${CMAKE_CURRENT_BINARY_DIR}/gstage.cir.sh ONLY_IF_DIFFERENT)
file(CHMOD ${CMAKE_CURRENT_BINARY_DIR}/gstage.cir.sh PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/modelcard.nmos ${CMAKE_CURRENT_BINARY_DIR}/modelcard.nmos ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/modelcard.pmos ${CMAKE_CURRENT_BINARY_DIR}/modelcard.pmos ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/opamp.cir ${CMAKE_CURRENT_BINARY_DIR}/opamp.cir ONLY_IF_DIFFERENT)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/opamp.cir.sh ${CMAKE_CURRENT_BINARY_DIR}/opamp.cir.sh ONLY_IF_DIFFERENT)
file(CHMOD ${CMAKE_CURRENT_BINARY_DIR}/opamp.cir.sh PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE)
file(COPY_FILE ${CMAKE_CURRENT_SOURCE_DIR}/tags ${CMAKE_CURRENT_BINARY_DIR}/tags ONLY_IF_DIFFERENT)
if( (NOT Xyce_PARALLEL_MPI) AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}ACtests/bsim4/gstage.cir.sh COMMAND perl -I${XyceRegressionTestScripts} gstage.cir.sh $<TARGET_FILE:Xyce> ${XYCE_VERIFY} ${XYCE_VERIFY} gstage.cir ${OutputDataDir}/ACtests/bsim4/gstage.cir.prn )
  set_property(TEST ${TestNamePrefix}ACtests/bsim4/gstage.cir.sh PROPERTY LABELS "serial;parallel;nightly;ac;bsim4;mos14;capacitor;esrc;resistor")
endif()
if( Xyce_PARALLEL_MPI  AND PERL_FOUND )
  add_test(NAME ${TestNamePrefix}ACtests/bsim4/gstage.cir.sh COMMAND perl -I${XyceRegressionTestScripts} gstage.cir.sh "mpiexec -bind-to none -np 2 $<TARGET_FILE:Xyce>" ${XYCE_VERIFY} ${XYCE_VERIFY} gstage.cir ${OutputDataDir}/ACtests/bsim4/gstage.cir.prn )
  set_property(TEST ${TestNamePrefix}ACtests/bsim4/gstage.cir.sh PROPERTY LABELS "serial;parallel;nightly;ac;bsim4;mos14;capacitor;esrc;resistor")
endif()
