This tutorial will show an example of how to add a very simple device model to Xyce. The demonstration model will implement a two-terminal device that simulates a simple series RLC combination. The tutorial will show one approach to adding this device: implementation of the compact model in Verilog-A, converting this model to C++ code that can be used in Xyce by using ADMS with the Xyce/ADMS back-end, and adding the new model to Xyce.
Direct implementation of the compact model in C++ and adding the new model to Xyce is more difficult, and requires a more thorough understanding of the Xyce code structure. This tutorial will not describe that technique. If you are interested in developing C++ compact models in Xyce, you should still review the Verilog-A method and look at the C++ source code it generates. Then consult the Doxygen documentation that can be generated in the doc/doxygen directory of the Xyce source tree. The "Circuit Device How To..." page in the Doxygen documentation describes the basic functions you must provide, and points you at the resistor and capacitor devices as sample implementations. The RLC device created through the Verilog-A translation process is another implementation example.
Note: The doxygen documentation is no longer provided in source tarballs, as it was determined that it inflated the download size and was of limited interest to most users, but may be generated if you have Doxygen and graphviz installed on your system. Simply type "doxygen Doxyfile" in the doc/doxygen directory, and it will produce files in the "html" subdirectory that may be browsed with a web browser (open html/index.html first).
In either case, you must be building Xyce from source code in order to add models to it. Xyce does have a limited beta capability using shared-library "plug-ins" to add models at run time, but building these plug-ins still requires access to the full Xyce source code tree because the plugin capability is not enabled by default and is not present in any binary release of Xyce.